1. Field of the Invention
The present invention relates to a MOS transistor having an improved sidewall of a gate electrode and a method for manufacturing the same.
2. Description of the Related Art
As a structure of a semiconductor device is patterned finer, parasitic capacitance which is inevitably present in an element structure gives rise to a larger problem. For example, the parasitic capacitance, which occurs between a gate electrode and a source/drain region which provides a MOS transistor, reduces an operating speed of the transistor and has a larger effect as the elements are patterned finer.
FIG. 7A shows part of a gate electrode structure of a conventional MOS transistor. Provided on a semiconductor substrate 111 such as silicon is a gate insulation film 112 such as a silicon oxide film, on which a gate electrode 113 is formed. A source/drain region 116 is formed in the semiconductor substrate 111. Side and upper surfaces of the gate electrode 113 are covered with a gate protecting insulation film (Sidewall Oxide Layer) 114, and the side surface of the protecting insulation film 114 is covered with a gate sidewall insulation film (Sidewall Spacer) 115 such as a silicon nitride film.
In the MOS transistor having such a configuration, the gate protection film 114 and the gate sidewall insulation film 115 are interposed as a dielectric between the gate electrode 113 and the source/drain diffusion region 116 (including a wiring layer thereof), so that there occurs unwanted parasitic capacitance.
Parasitic capacitance reduces the operating speed of the transistor. Especially in a fine-patterned transistor having a gate length of 0.2 μm or less, the parasitic capacitance reduces the operating speed greatly.
Furthermore, a MOS transistor having an elevated source/drain configuration shown in FIG. 7B has an elevated source/drain layer 117 which overlies the source/drain region 116 and is in contact with the gate sidewall spacer 115. This MOS transistor similarly suffers from drastic reduction in operating speed owing to large parasitic capacitance between the gate electrode 113 and the elevated source/drain layer 117 (including the wiring layer thereof) where the gate protection film 114 and the gate sidewall spacer 115 are interposed therebetween.
Although silicon oxide has been used as a material of the gate sidewall spacer conventionally, silicon nitride with high dielectric constant is used recently for a later-described reason. This has made the problem of parasitic capacitance further serious.
FIGS. 8A–8D and FIGS. 9A–9C show a method for manufacturing a MOS transistor in a case where a conventional gate sidewall spacer is made of silicon oxide.
As shown in FIG. 8A, after a gate oxide film 122 is formed on a silicon semiconductor substrate 121, a polysilicon film is deposited by Chemical Vapor Deposition (CVD) and processed by Reactive Ion Etching (RIE) to form a gate electrode 123 thereof.
As shown in FIG. 8B, an exposed surface of the gate electrode 123 is oxidized to form a gate protecting insulation film 124. Then, a part 125 of a source/drain diffusion region is formed in the semiconductor substrate 121 by ion implantation.
As shown in FIG. 8C, a silicon oxide film is deposited by CVD over the substrate surface and then removed by RIE to form a gate sidewall spacer 126 thereof. In this case, the exposed surface of the semiconductor substrate 121 is damaged by ions, so that a roughened exposed surface is formed on the one part 125 of the source/drain region.
As shown in FIG. 8D, a source/drain diffusion region 127 is formed in the semiconductor substrate 121 by ion implantation. In this case, since the surface of the semiconductor substrate 121 is roughened, variation in the shape of the diffusion regions occurs among the elements, which results in increased fluctuations in operating characteristics thereof.
As shown in FIG. 9A, the oxide film is removed from the upper surface of the gate electrode 123 using dilute hydrofluoric acid. In this case, the gate protection film 124 and the gate sidewall insulation film 126 are also removed partially. There are some cases where the insulation film 126 of the sidewall spacer is left little by a type of the MOS transistor formed on the semiconductor substrate 121. Next, as shown in FIG. 9B, a cobalt layer 128 is deposited over the substrate surface by sputtering.
As shown in FIG. 9C, a cobalt silicide layer 129 is provided on the gate electrode 123 and the source/drain region 127 by lamp heating. Thereafter, a non-reacted the cobalt layer is removed. In this case, in the MOS transistor in which the insulation film of the gate sidewall spacer is not almost left, the gate electrode 123 and the source/drain region 127 are electrically connected through the cobalt silicide layer 129, thereby reducing the yield.
To eliminate such a problem in this case of using the silicon oxide as the gate sidewall spacer, a silicon nitride film has been used as the gate sidewall spacer as shown in FIGS. 10A–10D and FIGS. 11A–11C.
After a gate oxide film 132 is formed on a semiconductor substrate 131 such as silicon, a gate electrode 133 such as a polysilicon film is formed thereon (FIG. 10A). Next, an exposed surface of the gate electrode. 133 is oxidized to form a gate protection insulation film 134. Then, a part 135 of a source/drain diffusion region is formed in the semiconductor substrate 131 by ion implantation (FIG. 10B). A silicon nitride film is deposited over the substrate surface by CVD and then selectively removed by RIE to provide a gate sidewall insulation spacer 136 on a side surface of the gate protection film 134.
According to the method, as shown in FIG. 11C, since the exposed face of the semiconductor substrate 131 can be prevented from being roughened, the shape of the source/drain diffusion region 137 does not vary among elements as shown in FIG. 10D. Therefore, it is possible to reduce fluctuations in operating characteristics of the elements.
Furthermore, as shown in FIG. 11A, the gate sidewall spacer is not removed during processing by use of dilute hydrofluoric acid, so that as shown in FIG. 11C the gate electrode 133 and the source/drain region 137 are not electrically connected, thereby preventing the yield from being deteriorated.
According to this method, however, since the dielectric constant of the gate sidewall spacer is about twice as large as that of the conventional silicon oxide film, the parasitic capacitance is roughly doubled, thus greatly reducing the operating speed of the element.
In this MOS transistor, a cobalt layer 138 is deposited over the surface of the semiconductor substrate 131 by sputtering (FIG. 11B). Then, using the lamp heating, a cobalt silicide layer 139 is formed on the gate electrode 133 and the source/drain region 137 (FIG. 11C) A non-reacted cobalt layer is removed.
The above-mentioned problem occurs also in a case of forming a MOS transistor having an elevated source/drain structure shown in FIGS. 12A–12D.
That is, FIGS. 12A–12D show a method for manufacturing a MOS transistor in a case of forming the gate sidewall spacer using the silicon oxide.
As shown in FIG. 12A, after a gate oxide film 142 is formed on a semiconductor substrate 141 such as silicon, a polysilicon film and a silicon nitride film are deposited consecutively by CVD and processed by RIE to form a gate electrode 143 and a silicon nitride film 144 sequentially.
As shown in FIG. 12B, after an exposed surface of the gate electrode 143 is oxidized to form a gate protection film 145, a part 146 of a source/drain diffusion region is formed in the silicon substrate by ion implantation.
As shown in FIG. 12C, a silicon oxide film is deposited over the surface of the semiconductor substrate 141 by CVD and then removed by RIE to form a gate sidewall spacer 147. In this case, the silicon semiconductor substrate is exposed partially and subjected to impact by ions, thereby providing a roughened surface thereon.
As shown in FIG. 12D, an elevated source/drain layer 148 is formed by epitaxial growth of silicon. In this case, a gap 150 called a facet is formed between the gate sidewall spacer 147 and the elevated layer 148.
A source/drain diffusion region 149 is formed in the semiconductor substrate 141 by ion implantation. In this case, a diffusion region under the facet is formed deep, so that it is difficult to control a threshold value of the transistor owing to the short-channel effect.
Therefore, a manufacturing method using a silicon nitride film is used as shown in FIGS. 13A–13D.
That is, as shown in FIG. 13A, after a gate oxide film 152 is formed on a semiconductor substrate 151 such as silicon, a polysilicon film and a silicon nitride film are deposited consecutively by CVD and processed by RIE to provide a gate electrode 153 and a silicon nitride film 154 sequentially.
As shown in FIG. 13B, after an exposed surface of the gate electrode 153 is oxidized to form a gate protection film 155, a part 156 of a source/drain diffusion region is formed in the silicon substrate 151 by ion implantation.
As shown in FIG. 13C, a silicon nitride film is deposited over the surface of the semiconductor substrate 151 by CVD and then removed from the flat portion by RIE to form a gate sidewall spacer 157.
According to the method, the surface of the semiconductor substrate in which the diffusion layer is formed is not roughened and, in addition, a gap called a facet is not formed between the gate sidewall spacer 157 and the elevated layer 158 as shown in FIG. 13D.
Therefore, the source/drain diffusion region is formed just as designed, so that the threshold value of the transistors can be controlled easily.
According to this method, however, the dielectric constant of the gate sidewall spacer is about twice as large as that of a conventional silicon oxide film, so that the parasitic capacitance is also doubled approximately, thus greatly reducing the operating speed of the elements.
As described above, to suppress variations in shape of the source/drain diffusion region thereby to prevent an undesired failure of short-circuiting at the time of salicide formation, a silicon nitride film is used as at least part of the gate sidewall spacer of the fine-patterned transistor. Furthermore, in the transistor having the elevated source/drain structure, the sidewall spacer of silicon nitride is used because of the facet formed at the time of the elevated layer formation. In addition, to prevent the semiconductor substrate from being dug at the time of forming the conductor plug connected to the source/drain region, the transistor is covered with a so-called liner film of a silicon nitride film.
Such silicon nitride present around these transistors has higher dielectric constant than silicon oxide and so increases the parasitic capacitance, thus greatly reducing the operating speed of the transistors. Furthermore, trapped charge, distortions, hydrogen, etc. present in the silicon nitride film cause fluctuations in characteristics of the transistors, thus reducing device reliabilities.